The data integrity requirements for personal computer systems have grown rapidly in the past few years. The speeds of personal computer central processing units ("CPU") and buses have steadily increased. For instance, speeds of 200 Mhz and 300 Mhz are currently achievable with CPUs attaining 1 GHz looming on the horizon. Furthermore, computer systems with bus speeds greater than 100 Mhz may tend to have a higher rate of data transmission errors when reading and writing to memory cards. This increase in errors occurs in part due to the increased noise of these systems. In these faster systems, while noise increases, the timing margin decreases. Computer systems that run at higher bus speeds provide less timing margin than slower systems. While the timing margin decreases in faster systems, and voltage is reduced to decrease power consumption, the higher speeds can increase the amount of noise generated by the system, and the reduced voltage can cause decreased noise margins. Furthermore, use of synchronous dynamic random access memory ("SDRAM") buses can exacerbate the problem of error occurrence due to noise. Thus, due to the increase of noise within a system, a dramatic increase in data errors can occur during data transmission, i.e., read and write cycles.
Moreover, the extra DRAM required for parity and error correction code ("ECC") can become prohibitively expensive for some markets. Also, since parity DRAMs are often produced in a different manner than other DRAMs, parity memory tends to be difficult to obtain. While parity is often eliminated from new computer systems, ECC is an inexpensive data error detection and correction mechanism. In many of today's standard computer systems, including the Pentium.TM. PRO microprocessor, ECC is built into the system.
These new systems with built-in ECC tend to have a 64 bit data bus with 8 check bits. Accordingly, while the means to control checkbits for ECC are provided by the system, many such systems do not include extra dynamic random access memory ("DRAM") that is required to support such checkbits. The existing DIMMs used in these systems, however, many times do not support ECC. Accordingly, a need exists to eliminate, or at least reduce, the high rate of data errors that can occur when these high speed systems read and write to memory cards. Also, a further need exists to utilize the ECC built-in to these computer systems.